Integrated circuit microprocessors must, in many cases, be connected with other integrated circuit devices in order to provide certain functions. Typically a microprocessor uses internal chip select circuitry to interface with other integrated circuits, often significantly reducing the cost of the system design and improving performance.
An example of an integrated circuit microprocessor with a highly flexible on-board chip select logic is taught by James B. Eifert et al. in U.S. Pat. No. 5,448,744, issued Sep. 5, 1995. The chip select logic taught by Eifert et al. provides a great deal of flexibility by allowing the chip select signal to be activated conditionally based on whether an attribute of an access cycle, such as whether the cycle is a read or a write cycle, matches a programmable attribute. This mechanism allows, for example, a program to be write protected by keeping the chip select signal inactive if the program erroneously attempts a write access to the area in memory where the program is stored.
A major concern associated with the integration of chip select logic onto a microprocessor integrated circuit involves the provision of sufficient flexibility to the user. The use of "glue" logic is extremely flexible, since the system designer has wide latitude in the placement of each external device with the microprocessor's memory map and the timing and other characteristics of the chip select signals themselves. This flexibility is very useful, since the variety of possible system designs and chip select requirements for particular peripheral devices is great. Providing sufficient flexibility in an integrated chip select unit while constraining the size of the unit within reasonable limits is quite difficult.
Peripheral devices have a variety of characteristics and requirements. One type of peripheral device operates synchronously with the microprocessor by use of both chip enable or chip select (CE) signals and output enable (OE) signals. Chip select signals are used to indicate the particular device to access, and output enable signals are used to synchronize the access. Device access therefore requires additional bus cycles to accomodate synchronization. Other devices have slow bus interface logic and require additional time after negation of CE, to allow for synchronout OE response and any number of functions particular to each device type. It is desireable to increase the flexibility of chip select signal timing in a data processing system to allow efficient system design for a broad range of peripheral devices.